The invention concerns ordering of line segments in a network. It is particularly applicable to the calculation of interferences between line segments in particularly dense electrical networks in which the structure of matrices involved has to be simplified as much as possible, for example, by making them as close as possible to diagonal matrices.
More generally, the invention is applicable to the ordering of line segments in any network in which it is required to determine interactions between lines.
The increase in the calculation power of computers and microcomputers has been made possible due to the emergence and maturity of the very large scale integration technology, such as microprocessors designed for general digital information processing purposes or for difficult special cases, for example, such as the generation of three-dimensional synthetic pictures.
However the development of the very large scale integration (VLSI) technique has introduced some drastic design constraints on interconnection support substrates, for example, such as printed circuits or thin film ceramics. In practice a direct result of these constraints is the use of thinner and thinner dielectric insulation and printed conductors on interconnection substrates in order to reasonably limit the thickness of printed circuits. The reductions in the size of conductors and the thickness of dielectric insulation has also been combined with an increase microprocessor operating frequency, for example reaching 50 MHz. In particular, the combination of the above developments has led to the risk of deformation of electrical signals and the creation of parasite signals due to interference between several conductors containing some portions very close to other conductors. It therefore becomes essential to predict the existence of interference or parasite generation between lines during the design stage of printed circuits or interconnection substrates. Since these circuits are laid out in very dense networks, it is frequently no longer possible to correct them after manufacture and during debugging.
Digital simulations exist to predict this type of parasite generation. For example, starting from the electrical excitation of a line in a network, the result of the simulation indicates the generation of current and voltages produced on other lines in the network. Nevertheless, these simulations have to take account of the propagation of parasites due to closer and closer interference on lines progressively further away from the initially disturbing lines or by multiple reflections, and involve many calculation sequences that are expensive in computer CPU occupation time and in memory space. This disadvantage is particularly due to the fact that these simulations involve calculations on very large matrices, the sizes of which are difficult to determine beforehand as a function of physically significant interferences, and these matrices must be inverted.
Another problem is due to the fact that, since network lines are broken down into segments defined by automatic conductor definition constraints, the breakdown thus obtained is never optimized for analysis of interferences and cannot give an efficient solution to the problem of propagation of incident and reflected disturbances.